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July 2004
AS91L1006BU
6-Port JTAG Gateway
Description
The AS91L1006BU is a one to 6-port JTAG gateway. It partitions a single JTAG chain into six separate chains. These separate chains can be optionally configured to operate as a single chain. The AS91L1006BU device is used to provide enhanced capabilities to the standard IEEE1149.1. It enables the IEEE1149.1 interface to be used in a true Multi-Drop environment without any additional signals. This Multi-Drop capability enables the standard IEEE1149.1 interface to be used not just for stand alone PCB (Printed Circuit Board) testing, but also for complete system testing including all PCBs within a system back plane environment. The AS91L1006BU provides the capability of partitioning the PCB, into multiple smaller IEEE1149.1 scan chains totally under software control. Partitioning the IEEE1149.1 chains on the PCB has several benefits which include easier fault diagnostics capabilities as a fault on one of the IEEE1149.1 Local Scan Ports (LSPs) does not render the PCB untestable, faster flash programming on the PCBs, and removal of IEEE1149.1 signal loading issues. All of the protocols required for addressing the AS91L1006BU device via the Multi-Drop capability and the protocols for configuring which of the six IEEE1149.1 LSPs on the AS91L1006BU are to be used, is handled via 3rd party ATPG tools from vendors like AssetIntertech and JTAG Technologies. In a Multi-Drop environment it is also possible to perform interconnect tests between multiple PCBs within a system thus extending the interconnect tests to the back plane itself.
Key Features
Device Multi-Drop addressable via the IEEE 1149.1 protocol Support for 6 local scan chains addressable via the IEEE 1149.1 interface Support for Pass-ThroughTM Support for the IEEE 1149.1 USERCODE instruction Support for Status instruction enabling nonintrusive monitoring of the system card Local Scan Port (LSP) enable signal provides the ability to use non IEEE 1149.1 compliant devices that require JTAG enable signal Provides the ability to initiate Self-Test on a remote PCB via a standard IEEE 1149.1 command Support for JTAG Technologies AutoWRTM feature Pinout and feature set compatible (complete second source) with the Firecron JTS06BU device Available in a 100-pin LQFP or a 100-pin FPBGA lead free package
Device Block Diagram
P a s s T h r o u g h E n a b le P r im a r y 1 1 4 9 . 1 J T A G In te rfa c e
LSP1
S ta tu s D a ta
LSP2
U s e rc o d e D a ta
1 1 4 9 . 1 T A P C o n t r o lle r and B o u n d a r y R e g is t e r S e le c t io n L o g ic
D e v ic e a d d re s s
P a s s T h ro u g h L o g ic & L o c a l S c a n P o rt C o n n e c t io n / C o n f ig lo g ic
LSP3
LSP4
D e v ic e S e le c t io n L o g ic
L o c a l S c a n P o rt P a r k /U n -p a rk S y n c L o g ic
LSP5
LSP6
Figure 1 - AS91L1006BU Device Block Diagram
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July 2004
AS91L1006BU
AS91L1006BU Gateway Functional Description
The basic structure of the AS91L1006BU device is shown in Figure-1. The core of the device is the 16-state IEEE1149.1 TAP controller state machine. All accesses to the internal registers of the AS91L1006BU device are controlled via this state machine during normal operation as per the IEEE1149.1 standard. The address selection logic enables the AS91L1006BU to operate in a MultiDrop environment within system backplane. The address selection logic compares the scanned address to the slot address value presented on the I/O of the AS91L1006BU device. The LSP park/unpark logic provides control through instructions scanned in under the IEEE1149.1 protocol, to select, which LSP will be placed into the active, scan chain. The passthrough and LSP connection logic selects the signal paths for the LSP IEEE1149.1 signals. The device also supports a Pass-Through mode which enables the primary IEEE1149.1 signals to be routed to any of the LSPs. This signal routing is selectable via I/O pins on the AS91L1006BU device. Figure-2 shows the device selection state machine. The AS91L1006BU will perform an address compare on the slot address presented at its I/O and the value scanned in via the IEEE1149.1. If the value matches then the AS91L1006BU becomes selected and is ready for normal access via IEEE1149.1 commands. If the address does not match then the device will proceed to the unselected mode, where it will remain until the AS91L1006BU is issued a GOTOWAIT instruction or a reset occurs via TRST or the LSP_RESET pin.
Selected Single Device
Device Unselected
Parked-RTI
Wait for Selection
Parked-TLR
ParkedPauseDR
UnParked
Select Group of Devices
Select All Devices
ParkedPauseIR
Figure 2 - AS91L1006BU Selection Logic State machine
Figure 3 - The LSP Park/Unpark State Machine
The LSP Park/Unpark State Machine controls the insertion of the LSPs into the current active scan chain. The ability to park the LSP in certain IEEE1149.1 states, enable the AS91L1006BU to perform several functions including backplane interconnect testing and IC BIST.
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AS91L1006BU
AS91L1006BU Detailed Mode of Operation
Addressing the AS91L1006BU device After a Test-Logic-Reset or power-up, the AS91L1006BU device will be in its Wait-forSelection state with its TDO pin tri-stated, thus avoiding contention in a Multi-Drop environment. The AS91L1006BU device will respond to a device-select sequence for a particular address that is auto generated by third party test tools with respect to the address that is pre-loaded on its S(5..0). Once this sequence has been completed, the AS91L1006BU device will respond to normal IEEE 1149.1 instructions. Note that addresses 6063 have been reserved and the AS91L1006BU device will not respond if the user selects these addresses. The AS91L1006BU device should be in the Wait-for-Selection mode, which can be entered into by issuing an asynchronous reset (through the deassertion of TRST) or by issuing a synchronous reset (through the assertion of TMS for five cycles of TCK). After the device has been selected, it can be issued a GOTOWAIT instruction. The internal IEEE1149.1 state machine of the AS91L1006BU device is taken to the Shift-IR phase and the required Device-ID is shifted into the Instruction register. As the IEEE1149.1 state machine passes through the Update-IR phase, the address is matched to the value on the S(5-0) pins on the AS91L1006BU device; if the values match, then the AS91L1006BU device is selected and is ready to receive any normal IEEE1149.1 command.
S(5-0) value < 3A hex or 60 decimal Table 1 - AS91L1006BU
IR (7 - 0) value XXVVVVVV Device Selection Table
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Table 2 - AS91L1006BU Multi Cast Group Selection Table Selection Mode Single Address Mode Binary Function Address XX000000 to Single AS91L1006BU XX111010 selected the TDO of the device will be active All accessible AS91L1006BU devices are selected for operation. TDO on all devices will be in HighZ Access all AS91L1006BU devices that have been placed in GRP0 by their MCGR contents Access all AS91L1006BU devices that have been placed in GRP1 by their MCGR contents Access all AS91L1006BU devices that have been placed in GRP2 by their MCGR contents Access all AS91L1006BU devices that have been placed in GRP3 by their MCGR contents
Table 3 - AS91L1006BU Device Register Description Register Name Instruction Register Description AS91L1006BU device addressing and instructiondecode IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 optional register IEEE Std. 1149.1 optional register AS91L1006BU device non intrusive 8-bit register pre load able from the I/O pins AS91L1006BU device specific single bit register for initiating self testing on a PCB AS91L1006BU device local-port configuration and control bits AS91L1006BU device Auto Write feature enable register AS91L1006BU device Async reset register for the LSPs
Broad XX111011 Cast Mode
Multi-Cast XX111100 Group 0
Multi-Cast XX111101 Group 1
BoundaryScan Register Bypass Register Device Identification Register User Code Register Status Register Self Test Register Mode Register Auto Write Register LSP Async Reset Register
Multi-Cast XX111110 Group 2
Multi-Cast XX111111 Group 3
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AS91L1006BU
Hex OpCode FF 00 81 AA E7 C5 84 C6 C3 8E 03 88 97 98 99 Binary Op- Data Register Code 11111111 Bypass Register 00000000 10000001 10101010 11100111 11000101 10000100 11000110 11000011 10001110 00000011 10001000 10010111 10011000 10011001 Boundary-Scan Register Boundary-Scan Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Mode Register Multi-Cast Group Register. Device Identification Register User Programmable 32 Bit Identification Register Auto Write Feature Enable Register Single bit low pulse, used to initiate function on PCB (SELF_TEST pin) User programmable status byte (USER_STATUS_DATA pins) Toggles LSP TRST while maintaining the AS91L1006BU in the selected state. Device Identification Register
Instructions BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT* MODESELECT MCGRSELECT SOFTRESET USERCODE AUTOWR STEST_PCB
STATUS_BYTE LSP_ASYNC_RESET
9A 9B
10011010 10011011
Other Undefined
TBD
TBD
Table 4 - AS91L1006BU Device Instruction Register OpCodes
Note: All instructions act on a single selected AS91L1006BU device only. * This instruction causes the AS91L1006BU to become unselected and revert to the Wait-forSelection state.
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AS91L1006BU
AS91L1006BU device Register descriptions
Bypass Register
It is a mandatory single bit register that can be connected between PRIM_TDI and PRIM_TDO of the AS91L1006BU device.
Multi-Cast Group Register
This 2-bit data register enables the host system to place the AS91L1006BU into one of four distinct addressable groups.
MCGR Register Bits [1..0] 00 01 10 11
Binary Selection Address XX111100 XX111101 XX111110 XX111111
MCGR GROUP GRP0 GRP1 GRP2 GRP3
Table 5 - Multicast Group Register Mapping Note: The MCGR is reset to 00 upon receiving TRST or the entering of the Test-Logic-Reset state.
IDCODE Register
It is an optional 32-bit register that can be connected between PRIM_TDI and PRIM_TDO of the AS91L1006BU device. The contents of the IDCODE register will be loaded with the following data when the AS91L1006BU enters Test-LogicReset or passes through Capture-IR: "00000000000000001000001101101111" Bits 0 to 11 indicate ALSC Jedec ID value of: "001101101111"
Bits 12 to 27 indicate the part number of the device: "0000000000010000" Bits 28 to 31 indicate the revision of the device: "0000"
USERCODE Register
The USERCODE is an 8-bit register that can be addressed via standard IEEE1149.1 commands, which are automatically generated by third party test tools. AS91L1006BU returns all zeroes if read from this registerUSERUSER and does have the ability to write into this register.
* The AS91L1006BU is a complete second source and pin for pin replacement of the Firecron JTS06BU device.
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AS91L1006BU
internal registers to be reset. In order to enable async reset tests on LSPs, the test tool should instruct the device to toggle the LSP reset pins while maintaining the set up information in the AS91L1006BU. When the instruction is loaded into the AS91L1006BU instruction register, a single bit data register is connected as the data register which is always reset to logic zero when the TAP state machine enters Capture-DR. This will cause the LSP TRST pins to pulse low for one TCK cycle, during the Update-DR phase.
SELF_TEST Register
The AS91L1006BU device supports a single output pin that can be controlled via the IEEE1149.1 interface. When the instruction is loaded into the AS91L1006BU instruction register, a single bit data register is connected which is always reset to logic zero when the TAP state machine enters Capture-DR. This will cause the SELF_TEST pin to pulse low for one cycle of TCK, during the Update-DR phase. This low going pulse can be used to initiate self-tests on PCB's in a rack via the JTAG interface.
AUTOWR Register LSP_ASYNC_RST Register
The AS91L1006BU device supports async reset tests on the devices connected to the LSPs. The standard method of performing these tests by utilizing the primary TRST pin cannot be used as it will cause the AS91L1006BU to deselect and its This is a 6-bit register that controls the passthrough of the JTAG Technologies AutoWRTM signal to any LSP. The register is reset to all zeros when entering the Test-Logic-Reset state.
Note: The MCGR is reset to 00 upon receiving TRST or the entering of the Test-Logic-Reset state AutoWr Register (Bit 2 - Bit 0) 000 001 011 100 101 110 111 LSP 3 AutoWr Signal High Z High Z High Z Active Active Active Active LSP 2 AutoWr Signal High Z High Z Active High Z High Z Active Active LSP 1 AutoWr Signal High Z Active Active High Z Active High Z Active AutoWr Register (Bit 5 - Bit 3) 000 001 011 100 101 110 111 LSP 6 AutoWr Signal High Z High Z High Z Active Active Active Active LSP 5 AutoWr Signal High Z High Z Active High Z High Z Active Active LSP 4 AutoWr Signal High Z Active Active High Z Active High Z Active
Table 6 - AUTOWR Register Mapping
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If the LSP is not parked in a stable state, i.e.: Pause-DR, Pause-IR, Run-Test-Idle or TestLogic-Reset, it will be connected into the active scan chain. If all LSPs are parked in a stable state, then the AS91L1006BU will perform a bypass of the 6-LSP chain section. In this way if both sections are in the bypass mode then the AS91L1006BU is performing a loopback of TDI>Register->TDO to the host device. Mode_Select Register (Bit 7 -> Bit 0) XXX0X000 XXX0X001 XXX0X010 XXX0X011 LSP Configuration (If Port Unparked) LSP_Data ->TDO LSP_Data ->LSP4->PAD>TDO LSP_Data ->LSP5->PAD>TDO LSP_Data ->LSP4->PAD>LSP5->PAD->TDO LSP_Data ->LSP6->PAD>TDO LSP_Data ->LSP4->PAD>LSP6->PAD->TDO LSP_Data ->LSP5->PAD>LSP6->PAD->TDO LSP_Data ->LSP4->PAD>LSP5->PAD->LSP6->PAD>TDO
MODE_SELECT Register
The Mode_Select register allows the LSP of the AS91L1006BU to be connected in various different configurations. A LSP is selected for connection within the scan chain by the contents of the Mode_Select register.
Mode_Select Register (Bit 15 -> Bit 8) XXX0X000 XXX0X001 XXX0X010 XXX0X011
LSP Configuration (If Port Unparked) TDI ->Register->LSP_Data TDI ->Register->LSP1->PAD-> LSP_Data TDI ->Register->LSP2->PAD-> LSP_Data TDI ->Register->LSP1->PAD>LSP2->PAD-> LSP_Data TDI ->Register->LSP3->PAD-> LSP_Data TDI ->Register->LSP1->PAD>LSP3->PAD-> LSP_Data TDI ->Register->LSP2->PAD>LSP3->PAD-> LSP_Data TDI ->Register->LSP1->PAD>LSP2->PAD->LSP3->PAD-> LSP_Data
XXX0X100 XXX0X101
XXX0X100 XXX0X101
XXX0X110
XXX0X110
XXX0X111
XXX0X111
Table 7 - Mode Select Register Mapping X = Don't care Register = AS91L1006BU device instruction register or any of the AS91L1006BU device test data registers. PAD = Insertion of a 1-bit register for data synchronization. Upon entering Test-Logic-Reset, the register bits will be loaded with "0000000".
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AS91L1006BU
Pass Through Support within the AS91L1006BU Device
The AS91L1006BU device supports a Pass-Through mode where the primary or master IEEE1149.1 JTAG signals can be routed to any one of the LSPs. When this mode is activated, the "Debug Enable" signal for that LSP will go active, which can be used to place a processor such as the MPC8260 into BDM (Background Debug mode), if required. If no processors are present in the LSP, the Pass-Through mode can be used to assist in the generation of the test vectors or memory tests for the devices that are linked into the selected LSP. The pass-through feature has the effect of simplifying the test vector generation for the LSP, as it also has the effect of removing the AS91L1006BU device from the test vector generation process.
PASS_THRU_Enable PASS_THRU_SEL(2) PASS_THRU_SEL(1) PASS_THRU_SEL(0) Active LSP High Low Low Low Low Low Low X Low Low Low Low High High X Low Low High High Low Low X Low High Low High Low High Normal Operation LSP1 LSP2 LSP3 LSP4 LSP5 LSP6
Table 8 - Pass through mode in AS91L1006BU Note: When PASS_THRU_ENABLE is deasserted (logic "1"), then the LSPs are under control of the AS91L1006BU device logic. When PASS_THRU_ENABLE is asserted (logic "0") and if an invalid combination is presented on the PASS_THRU_SEL lines, then all LSPs are tri-stated.
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Signal Description
PIN NAME LSP1_TCK PIN TYPE OUT PIN NUMBER LQFP 31 PIN DESCRIPTION NUMBER FPBGA H4 IEEE1149.1 Test Clock on LSP 1 when PASS_THRU_ENABLE is HIGH. Stable state after port/reset Buffered version of signal present on primary TCK
LSP1_TMS
OUT
32
J4
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 1 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. IEEE1149.1 Test Reset on LSP 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is tri-stated for all other combinations.
LSP1_TDO
OUT
35
H5
LSP1_TDI
IN
33
K4
LSP1_TRST
OUT
29
K3
Buffered version of signal present on primary TRST
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PIN NUMBER LQFP 30 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA J3 Flash, Memory Auto-Write on LSP 1 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. Pass-Through Debug Enable Output Logic '1' on Local Scan Port 1. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 000. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 2 when PASS_THRU_ENABLE is HIGH.
PIN NAME LSP1_AutoWR
PIN TYPE OUT
LSP1_DE
OUT
28
J2
LSP2_TCK
OUT
41
J6
Buffered version of signal present on primary TCK
LSP2_TMS
OUT
42
H6
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 2 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 2 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations.
LSP2_TDO
OUT
45
J7
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PIN NUMBER LQFP 44 PIN DESCRIPTION NUMBER FPBGA K7 IEEE1149.1 Test Data In on LSP 2 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. IEEE1149.1 Test Reset on LSP 2 when PASS_THRU_ENABLE is HIGH.
PIN NAME LSP2_TDI
PIN TYPE IN
Stable state after port/reset
LSP2_TRST
OUT
37
K5
Buffered version of signal present on primary TRST
LSP2_AutoWR
OUT
40
K6
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 2 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 2. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 001. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations.
LSP2_DE
OUT
36
J5
LSP3_TCK
OUT
49
K9
Buffered version of signal present on primary TCK
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PIN NUMBER LQFP 50 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA K10 IEEE1149.1 Test Mode Select on Logic '1' LSP 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 3 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. IEEE1149.1 Test Reset on LSP 3 when PASS_THRU_ENABLE is HIGH.
PIN NAME LSP3_TMS
PIN TYPE OUT
LSP3_TDO
OUT
53
H10
LSP3_TDI
IN
52
J10
LSP3_TRST
OUT
47
J8
Buffered version of signal present on primary TRST
LSP3_LSP_ AutoWR
OUT
48
K8
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 3 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations.
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PIN NUMBER LQFP 46 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA H7 PASS_THRU Debug Enable Output Logic '1' on LSP 3. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 010. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 4 when PASS_THRU_ENABLE is HIGH.
PIN NAME LSP3_DE
PIN TYPE OUT
LSP4_TCK
OUT
79
A8
Buffered version of signal present on primary TCK
LSP4_TMS
OUT
78
A9
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 4 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 4 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 4 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011.
LSP4_TDO
OUT
76
B10
LSP4_TDI
IN
77
B9
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PIN NUMBER LQFP 81 PIN DESCRIPTION NUMBER FPBGA A7 IEEE1149.1 Test Reset on LSP 4 when PASS_THRU_ENABLE is HIGH.
PIN NAME LSP4_TRST
PIN TYPE OUT
Stable state after port/reset Buffered version of signal present on primary TRST
LSP4_AutoWR
OUT
80
B8
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 4 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 4. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 011. This pin is high for all other combinations. IEEE1149.1 Test Clock on LSP 5 when PASS_THRU_ENABLE is HIGH.
LSP4_DE
OUT
83
B7
LSP5_TCK
OUT
70
D10
Buffered version of signal present on primary TCK
LSP5_TMS
OUT
69
D9
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 5 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations.
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PIN NUMBER LQFP 67 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA E8 IEEE1149.1 Test Data Out on LSP 5 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 5 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. IEEE1149.1 Test Reset on LSP 5 when PASS_THRU_ENABLE is HIGH.
PIN NAME LSP5_TDO
PIN TYPE OUT
LSP5_TDI
IN
68
E7
LSP5_TRST
OUT
72
C9
Buffered version of signal present on primary TRST
LSP5_AutoWR
OUT
71
D8
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is tri-stated for all other combinations. Flash, Memory Auto-Write on LSP 5 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 5. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 100. This pin is high for all other combinations.
LSP5_DE
75
C10
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AS91L1006BU
PIN NUMBER LQFP 61 PIN DESCRIPTION NUMBER FPBGA F10 IEEE1149.1 Test Clock on LSP 6 when PASS_THRU_ENABLE is HIGH.
PIN NAME LSP6_TCK
PIN TYPE OUT
Stable state after port/reset Buffered version of signal present on primary TCK
LSP6_TMS
OUT
60
F9
Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Logic '1' LSP 6 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on LSP 6 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on LSP 6 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. IEEE1149.1 Test Reset on LSP 5 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is tri-stated for all other combinations.
LSP6_TDO
OUT
57
G10
LSP6_TDI
IN
58
G8
LSP6_TRST
OUT
64
E9
Buffered version of signal present on primary TRST
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AS91L1006BU
PIN NUMBER LQFP 63 PIN Stable state DESCRIPTION NUMBER after port/reset FPBGA F7 Flash, Memory Auto-Write on LSP 6 Logic '1' when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101; PRIM_AutoWR is routed to output. This pin is tri-stated for all other combinations. PASS_THRU Debug Enable Output Logic '1' on LSP 6. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[2:0] = 101. This pin is high for all other combinations. IEEE1149.1 Primary Test Clock Input. IEEE1149.1 Primary Test Mode Select Input. IEEE1149.1 Primary Test Data Output. This pin is tri-stated when AS91L1006BUis not selected. IEEE1149.1 Primary Test Data Input IEEE1149.1 Primary Test Reset Input.
PIN NAME LSP6_AutoWR
PIN TYPE OUT
LSP6_DE
OUT
65
E10
PRIM_TCK PRIM_TMS PRIM_TDO
IN IN OUT
87 21 20
A6 G2 G1
HighZ
PRIM_TDI PRIM_TRST
IN IN
19 22
G3 H2
PRIM_AutoWR
IN
S[5:0]
IN
This active low asynchronous reset input signal places AS91L1006U in Wait-for-Selection state. 16 F1 Primary Auto-Write Input controlled by test equipment to shorten Flash memory programming. 8,7,6,5,100, D2,D1,D3,C AS91L1006BU Slot Address[5:0] 99 2,B2,A2 Inputs. Used to set address at which AS91L1006BU will respond; typically set by hardwired connection on the backplane. Test Output Enable Input. Tri-states all LSPs, when asserted low.
*TOE
IN
88
B6
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AS91L1006BU
PIN NUMBER LQFP 14 PIN DESCRIPTION NUMBER FPBGA F4 LSP Reset Input.
PIN NAME LSP_RESET_n
PIN TYPE IN
Stable state after port/reset
AS91L1006BU_ SELECTED
OUT
25
K1
Active low resets AS91L1006BU to "Wait-for-Selection" state and pulses all LSP TRST output pins to low. This resets all devices with TRST function; typically this signal would be connected to a power-on-reset function. AS91L1006BU_Selected Output. Logic '1' Active low when AS91L1006BU is selected; typically used to control off board buffering. LSP Enabled Output. Logic '1'
LSP_ENABLE
OUT
24
J1
USER_STATUS _BYTE[7:0]
IN
SELF_TEST
OUT
PASS_THRU_ ENABLE
IN
Active low when AS91L1006BU is selected; typically used to set IEEE1149.1 compliance enable pins on devices. 84, 85, 92, C7,C6,C5,C AS91L1006BU Status_Byte Inputs. 93, 94, 96, 4,B4,A4,B3, 97, 98 A3(MSB- Used to provide status information of (MSB-LSB) LSB) the PCB under test back to the test master via the IEEE1149.1 bus. Eight signals levels can be monitored and then reported via the IEEE1149.1 bus in a non intrusive manner. 27 K2 Provides a low going output pulse Logic '1' under command from the IEEE1149.1 bus, which can be used to start self-test functions on a PCB. 9 E4 PASS_THRU Enable Input. Active high disables Pass-Through mode. Active low enables Pass-Through mode. 13,12,10 E2,E1,E3 PASS_THRU Select Inputs. (MSB-LSB) (MSB-LSB) Used to select active routing of PassThrough ports enabled by active low on PASS_THRU_ENABLE pin. 000 = LSP1 001 = LSP2 010 = LSP3 011 = LSP4 100 = LSP5 101 = LSP6
PASS_THRU_ SEL12:0]
IN
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AS91L1006BU
PIN NUMBER LQFP 38, 86, 11, 26, 43, 59, 74, 95, 2, 17, 54, 55 90 PIN DESCRIPTION NUMBER FPBGA D6, G5, C3, Ground pins. D7, E5, F6, G4,H8, H9, J9,B1, A5, F2
PIN NAME GND
PIN TYPE POWER
Stable state after port/reset
VCC
POWER
39, 91, 3, D5, G6, C8, VCC pins. 18, 34, 51, D4, E6, F5, 66, G7, 82,23,56 H3,G9,H1 89 B5 Factory Test_Enable Input. This pin should be left unconnected. IEEE1149.1 ASIC Test Clock Input. IEEE1149.1 ASIC Test Mode Select. Input IEEE1149.1 ASIC Test Clock Output. IEEE1149.1 ASIC Test Clock Input.
ASIC_TEST_ EN ASIC_TCK ASIC_TMS ASIC_TDO ASIC_TDI No Connects
IN
IN IN OUT IN
62 15 73 4 1
F8 F3 A10 A1 C1
Table 9 - AS91L0006BU Signal Description
Absolute Maximum Ratings
Parameter Supply Voltage (Vcc) DC Input Voltage (Vi) Max sink current when Vi = -0.5V Max source current when Vi = Vcc + 0.5V Max Junction Temperature with power applied Tj Max Storage temperature Maximum Range -0.3V to 5.5V -0.5V to Vcc +0.5V -20mA +20mA +125 degrees C -55 to +150 degree C
Table 10 - Absolute Maximum Ratings Note: Stress above the stated maximum values may cause irreparable damage to the device. Correct operation of the device at these values is not guaranteed.
Recommended Operating Conditions
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AS91L1006BU
Parameter Supply Voltage (Vcc) Input Voltage (Vi) Output Voltage (Vo) Operating Temperature (Ta) Commercial Industrial (Ta)
Operating Range 3.0V to 3.6V 0V to Vcc 0V to Vcc 0 C to 70 C -40 deg C to +85 deg C, 3.00V to 3.6V
Table 11 - Recommended Operating Conditions
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AS91L1006BU
AC Electrical Characteristics
Tch TCK Tsu Th Tcl Tcw
TMS
TDI Toe Tco TDO Tpd Lsp Signal High Z High Z
Figure 4 - AS91L1006BU AC Timing Diagram SYMBOL Parameter Tcw Tch Tcl Tsu Th Toe Tco Tpd TCK clock pulse width TCK pulse width high TCK pulse width low TCK Setup time TCK Hold time Neg Edge TCK to valid data enable Neg Edge TCK to valid data Pass through Mode Primary/Lsp Delay MIN 100 50 50 30 40 20 15 MAX 10 UNITS ns ns ns ns ns ns ns ns
Table 12 - AS91L1006BU AC Timing Information
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AS91L1006BU
DC Electrical Characteristics
Symbol VIH VIL Symbol VOH VOL Ioz Icc Iccd Parameter Minimum High Input Voltage Maximum Low Input Voltage Parameter Minimum High Output Voltage Minimum LowOutput Voltage Max 5.25 0.8V Value 2.4V 0.4V Min 2.0 -0.3V Condition Ioh=24mA or 8mA as defined by pin Iol=24mA or 8mA as defined by pin Condition
Tristate output leakage -10 or 10 mA Maximum quiecennt supply current Maximum dynamic supply current 2mA 80mA TCK freq equal to 10 MHz
Table 13 - AS91L1006BU DC Electrical Characteristics
Packaging Information
The AS91L1006BU is available in a 100-pin LQFP or a 100-pin FPBGA lead free package.
SYMBOL
LE AD S
TO L.
MAX.
100 LEAD
1 .6 0
1
A
D Square
A
A
D
D
1
2
M IN
M IN
MAX
MAX
0 .0 5
1 .3 5 1 .4 0
0 .1 5
1 .4 5
NOM
B A S IC
1 8 .0 0
1 4 .0 0
1
B A S IC
D1 Square
L
0 .1 5
0 .6 0
L1
REF
1 .0 0
b
M IN
MAX
0 .1 7
0 .2 7
e
B A S IC
0 .5 0
ccc
MAX
0 .0 8
ddd
NOM
JED EC R EF #
0 .0 8
M S -0 2 6
3
NOTES : 1. ALL LIN EAR DIM ENSIO NS ARE IN M ILLIM E TE RS . 2. PLAS TIC BO DY D IM EN SIO NS DO N O T INC LU DE FLAS H O R PR O TUSIO N . M AX ALLO W ABLE 0.25 PER SIDE. 3. LEAD C O UN T O N D RA W ING N O T RE PRESENTATIVE O F A CTUAL PACKAG E.
12 NOM
A
0-7 TYP
A1
A2
-C0.09/0.20 TYP
A
e
0.25
L1 L
b
CCC LEAD COPLANARITY al al al M A-B S DS
12 NOM
Figure 5 - LQFP-100
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AS91L1006BU
D 2
A B
REV. A B
Revisions DESCRIPTION Initial document release. Updated ball coplanarity limits from 0.20mm to 0.15mm.
ECN 91253
DATE 12-04-01
E
C
0.15 C
D1
K I H G F E D C B A 1 2 3 4 5 6 7 8 9 10
E1
SYMBOL A A1 A2 b D D1 E E1 e PACKAGE NUMBER JEDEC REF #
DIMENSIONS MIN. -0.30 0.25 0.50
NOM. ---0.60 11.00 BSC 9.00 BSC 11.00 BSC 9.00 BSC 1.00 FBGA0100-11F MO-192 VAR. AAC-1
MAX. 1.70 -1.10 0.70
b
0.25 M 0.25 M
CAB C
Figure 6 - FPBGA-100
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AS91L1006BU
Device Selector Guide and Ordering Information
AS91L
Aliance Semiconductor system solution
XXXX
UU - CC PP - TEMP - L
Blank = leaded F = lead free G = green
C = Commercial (0 to 70 degrees C) I = Industrial (-40 to 85 degrees C) Package L100 = 100 pin LQFP F100 = 100 pin FPBGA Clock speed 10 = 10 MHz TCK 40 = 40 MHz TCK
Device family 1001 1002 1003 1006 Product version S = standard U = 16-bit user code BU = 8-bit status/user code E = enhanced
Figure 7 - Part Numbering Guide
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AS91L1006BU
Part Number AS91L1006BU - 10L100-C AS91L1006BU - 10L100-CF AS91L1006BU - 10L100-I AS91L1006BU - 10L100-IF AS91L1006BU - 10F100-C AS91L1006BU - 10F100-CG AS91L1006BU - 10F100-I AS91L1006BU - 10F100-IG AS91L1006BU - 40L100-CF
Description JTAG 6-Port Gateway, 100-pin LQFP package, commercial JTAG 6-Port Gateway, 100-pin LQFP package, commercial, lead free JTAG 6-Port Gateway, 100-pin LQFP package, industrial JTAG 6-Port Gateway, 100-pin LQFP package, industrial, lead free JTAG 6-Port Gateway 100-pin FPBGA package, commercial JTAG 6-Port Gateway 100-pin FPBGA, commercial, green package JTAG 6-Port Gateway 100-pin FPBGA package, industrial JTAG 6-Port Gateway 100-pin FPBGA, industrial, green package JTAG 6-Port Gateway, 100-pin LQFP package, commercial, lead free, 40 MHz TCK JTAG 6-Port Gateway, 100-pin LQFP package, industrial, lead free, 40 MHz TCK JTAG 6-Port Gateway 100-pin FPBGA, commercial, green package, 40 MHz TCK JTAG 6-Port Gateway 100-pin FPBGA, industrial, green package, 40 MHz TCK
AS91L1006BU - 40L100-IF
AS91L1006BU - 40F100-CG AS91L1006BU - 40F100-IG
Table 14 - Valid Part Number Combinations
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AS91L1006BU
Device Master AS91L1001 AS91L1002 AS91L1003U AS91L1006BU
Description
FPBGA-100 (1mm pitch)
Package Options
LQFP-100
JTAG Test Controller JTAG Test Sequencer 3-Port Gateway 6-Port Gateway
x x x x
x x x x
Table 15 - JTAG Controller Product Family
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AS91L1006BU
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